Design Verification Engineer
Job position: Design Verification Engineer, Austin, TX, USA
: Developed and implemented SystemVerilog and UVM (Universal Verification Methodology) based testbenches, simulation environments...) GLS, NLP, XPROP simulation experience is required Strong proficiency in system verilog assertions, constraints..
Job Location: Austin, TX, USASalary: unspecified
Company: Advanced Micro Devices
Job posted: 11 Feb 2026
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