ASIC Design Verification Engineer (ASIC / Hardware)
Job position: ASIC Design Verification Engineer (ASIC / Hardware), Santa Clara, CA, USA
production Expertise in SystemVerilog and UVM Required strengths Defining test plans, including comprehensive adversarial... and independence in planning, debugging complex failures, closing metrics-driven tasks, driving vendors, and reporting status.....
Job Location: Santa Clara, CA, USASalary: $101000 - 164000 per year
Company: Palo Alto Networks
Job posted: 06 Feb 2025
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