Design Verification Engineers
Job position: Design Verification Engineers, Austin, TX, USA
and CHI interfaces C/C++ Synopsys tools, VCS, VC Formal Python based simulation flow Wide Vector Unit and a Matmul Unit.... Formal verification SOC System integration is also required, like booting Linux OS GLS (Gate Level Simulation) Low Power..
Job Location: Austin, TX, USASalary: unspecified
Company: TekWissen
Job posted: 18 Feb 2026
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