SystemVerilog/UVM and/or VHDL; Develop constrained-random, metric-driven test plans and strategies to verify FPGAs performing...-checking testbenches in SystemVerilog/UVM, OVM, and/or VHDL Experience with FPGA/ASIC design and verification tools (Mentor.....
Job Location: Manchester, NH, USASelected articles on work and employment, which may be found interesting:
How to Find a Proper Job Searching Service?Find more articles on Articles page