Senior E/E & Semiconductor Engineer - CAD/EDA – Silicon Design/Verification Infrastructure Engineer
Job position: Senior E/E & Semiconductor Engineer - CAD/EDA – Silicon Design/Verification Infrastructure Engineer, San Francisco, CA, USA
Job Summary: We are seeking a skilled CAD Infrastructure Lead to support our ASIC design team. The ideal candidate... and environments to support ASIC design and verification processes. Support Design Teams: Provide technical support to design teams.....
Job Location: San Francisco, CA, USASalary: unspecified
Company: Capgemini
Job posted: 02 Feb 2025
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