FE Signoff Engineer
Job position: FE Signoff Engineer, Austin, TX, USA
Verification Engineer to help develop a Gate Level Simulation methodology as a template for organizations across the company... Understanding of Simulation tools and how to maximize their performance. Knowledge of UVM verification methodology, assertions.....
Job Location: Austin, TX, USASalary: unspecified
Company: Ericsson
Job posted: 26 Nov 2024
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