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FPGA DSP Firmware Design Engineer


Job position: FPGA DSP Firmware Design Engineer, Rancho Santa Fe, CA, USA

descriptor languages, HDL (VHDL, Verilog), based on customer requirements and/or MATLAB model(s). Collaborate with a multi..., design, and implement HDL test benches in hardware description languages, HDL (VHDL, Verilog), for code validation.....

Job Location: Rancho Santa Fe, CA, USA

Salary: $65000 - 117500 per year

Company: Leidos

Job posted: 01 May 2024

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