Senior Low power logic design Engineer
Apple
- San Diego, CA
- Permanent
- Full-time
- We'd like you to have:
- Proved track record in power/clock management logic design
- Proficiency in Verilog language
- SoC level power management logic verification and debug experience
- Deep understanding of ASIC low power design techniques
- Knowledge of CDC, RDC and UPF and its VCLP checker
- Strong problem solving
- Proficiency in scripting languages, e.g. Unix shell, Perl or Python
- SoC top-level integration experience is a plus
- SW team support experience is a plus
- System architecture knowledge is a plus
- Post-silicon debug experience is a plus